Modeling the sensitivity of CMOS circuits to radiation induced single event transients
GI Wirth, MG Vieira, EH Neto, FL Kastensmidt - Microelectronics reliability, 2008 - Elsevier
An accurate and computer efficient analytical model for the evaluation of integrated circuit
sensitivity to radiation induced single event transients is presented. The key idea of the work …
sensitivity to radiation induced single event transients is presented. The key idea of the work …
Generation and propagation of single event transients in CMOS circuits
GI Wirth, MG Vieira, EH Neto… - 2006 IEEE Design and …, 2006 - ieeexplore.ieee.org
The generation and the propagation of radiation induced single event transients (SET) in
CMOS circuits are evaluated. An accurate and computer efficient analytical model for SET …
CMOS circuits are evaluated. An accurate and computer efficient analytical model for SET …
Accurate and computer efficient modelling of single event transients in CMOS circuits
GI Wirth, MG Vieira, FGL Kastensmidt - IET Circuits, Devices & Systems, 2007 - IET
A new analytical modelling approach to evaluate the impact of single event transients
(SETs) on CMOS circuits has been developed. The model allows evaluation of transient …
(SETs) on CMOS circuits has been developed. The model allows evaluation of transient …
Transistor sizing for radiation hardening
Q Zhou, K Mohanram - 2004 IEEE International Reliability …, 2004 - ieeexplore.ieee.org
This paper presents an efficient and accurate numerical analysis technique to simulate
single event upsets (SEUs) in logic circuits. Experimental results that show the method is …
single event upsets (SEUs) in logic circuits. Experimental results that show the method is …
Single event transients in combinatorial circuits
GI Wirth, MG Vieira, EH Neto… - Proceedings of the 18th …, 2005 - dl.acm.org
The single event upset (SEU) mechanism in MOS circuits is normally investigated by Spice-
like circuit simulation. The problem is that electrical simulation is time consuming and must …
like circuit simulation. The problem is that electrical simulation is time consuming and must …
An overview of the modeling and simulation of the single event transients at the circuit level
M Andjelkovic, A Ilic, Z Stamenkovic… - 2017 IEEE 30th …, 2017 - ieeexplore.ieee.org
The single event transients (SETs) are a common source of malfunction in nano-scale
CMOS integrated circuits. For this reason, evaluation of the SET effects and application of …
CMOS integrated circuits. For this reason, evaluation of the SET effects and application of …
Modeling ion-induced pulses in radiation-hard SOI integrated circuits
DE Fulkerson, DK Nelson, RM Carlson… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
A common technique for hardening a circuit cell against single-event effects (SEE) is to use
an RC delay or other time delay technique to slow down the response of a storage or …
an RC delay or other time delay technique to slow down the response of a storage or …
Modeling single event transients in advanced devices and ICs
The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs)
was predicted for the first time by Wallmark and Marcus in the early 60's and was confirmed …
was predicted for the first time by Wallmark and Marcus in the early 60's and was confirmed …
A fast, analytical estimator for the SEU-induced pulse width in combinational designs
Single event upsets (SEUs) are becoming increasingly problematic for both combinational
and sequential circuits with device scaling, lower supply voltages and higher operating …
and sequential circuits with device scaling, lower supply voltages and higher operating …
Single event effects on digital integrated circuits: Origins and mitigation techniques
New generation electronic devices have become more and more sensitive to the effects of
the natural radiation coming from the surrounding environment. These radiation sources are …
the natural radiation coming from the surrounding environment. These radiation sources are …