A single-poly PMOS nonvolatile memory (NVM) cell and a method of programming, erasing
and reading such a cell are implemented using a single-poly PMOS NVM cell which …

US5912842A - Nonvolatile PMOS two transistor memory cell and array - Google Patents
US5912842A - Nonvolatile PMOS two transistor memory cell and array - Google Patents …

A row decoder circuit selectively provides suitable programming, reading, and erasing
voltages to an associated memory array employing PMOS floating gate transistors as …

A non-volatile memory (NVM) cell splits its basic function, ie program, erase, read and
control, among a four PMOS transistor structure, allowing independent optimization of each …

A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control
gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area …

A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control
gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area …

A nonvolatile PMOS memory array includes a plurality of pages, where each column of a
page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS …

A novel structure of nonvolatile memory is disclosed. The non-volatile memory includes two
serially connected PMOS transistors. The characteristic of the devices is that bias is not …

PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS
floating gate transistor com prises a floating gate and a gate oxide layer between the floating …

A P-channel single-poly non-volatile memory cell having P+ source and P+ drain regions
and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon …