The exponential increase in leakage power due to technology scaling has made power
gating an attractive design choice for low-power applications. In this paper, we explore this …

While some leakage power reduction techniques require modification of the process
technology, others are based on circuit-level optimizations and are applied at run-time. We …

This paper describes a power gating technique with multiple sleep modes where each mode
represents a trade-off between wake-up overhead and leakage savings. We show that high …

For the most recent CMOS feature sizes (eg, 90nm and 65nm), leakage power dissipation
has become an overriding concern for VLSI circuit designers. ITRS reports that leakage …

Power-gating is a technique for saving leakage power by shutting off the idle blocks.
However, without good understanding and careful design, negative effects of power gating …

Leakage power consumption of current CMOS technology is already a great challenge.
International Technology Roadmap for Semiconductors projects that leakage power …

Power gating is a technique commonly used for leakage reduction in integrated circuits. In
microprocessors, power gating is implemented by using sleep transistors to selectively …

Leakage power dissipation becomes a dominant component in operation power in
nanometer devices. This paper describes a design methodology to implement runtime …

In this paper we focus on leakage reduction through automatic insertion of sleep transistors
using a row-based granularity. In particular, we tackle here the two main issues involved in …

Power gating is one of the most effective techniques in reducing leakage power, which
increases exponentially with device scaling. However, large ground bounces during abrupt …