Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation

J Renau, J Tuck, W Liu, L Ceze, K Strauss… - Proceedings of the 19th …, 2005 - dl.acm.org
Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support
Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must …

POSH: a TLS compiler that exploits program structure

W Liu, J Tuck, L Ceze, W Ahn, K Strauss… - Proceedings of the …, 2006 - dl.acm.org
As multi-core architectures with Thread-Level Speculation (TLS) are becoming better
understood, it is important to focus on TLS compilation. TLS compilers are interesting in that …

Thread-level speculation on a CMP can be energy efficient

J Renau, K Strauss, L Ceze, W Liu, S Sarangi… - Proceedings of the 19th …, 2005 - dl.acm.org
Chip Multiprocessors (CMP) with Thread-Level Speculation (TLS) have become the subject
of intense research. However, TLS is suspected of being too energy inefficient to compete …

[图书][B] Hardware support for thread-level speculation

JG Steffan - 2003 - search.proquest.com
Novel architectures that support multithreading, for example chip multiprocessors, have
become increasingly commonplace over the past decade: examples include the Sun MAJC …

The STAMPede approach to thread-level speculation

JG Steffan, C Colohan, A Zhai, TC Mowry - ACM Transactions on …, 2005 - dl.acm.org
Multithreaded processor architectures are becoming increasingly commonplace: many
current and upcoming designs support chip multiprocessing, simultaneous multithreading …

Multiplex: Unifying conventional and speculative thread-level parallelism on a chip multiprocessor

CL Ooi, SW Kim, I Park, R Eigenmann… - Proceedings of the 15th …, 2001 - dl.acm.org
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit,
threading in which the hardware employs prediction to peel off instruction sequences (ie …

Combining thread level speculation helper threads and runahead execution

P Xekalakis, N Ioannou, M Cintra - Proceedings of the 23rd international …, 2009 - dl.acm.org
With the current trend toward multicore architectures, improved execution performance can
no longer be obtained via traditional single-thread instruction level parallelism (ILP), but …

A scalable approach to thread-level speculation

JG Steffan, CB Colohan, A Zhai, TC Mowry - ACM SIGARCH Computer …, 2000 - dl.acm.org
While architects understand how to build cost-effective parallel machines across a wide
spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real …

Exposing speculative thread parallelism in SPEC2000

MK Prabhu, K Olukotun - Proceedings of the tenth ACM SIGPLAN …, 2005 - dl.acm.org
As increasing the performance of single-threaded processors becomes increasingly difficult,
consumer desktop processors are moving toward multi-core designs. One way to enhance …

[PDF][PDF] Hardware and software support for speculative execution of sequential binaries on a chip-multiprocessor

V Krishnan, J Torrellas - … of the 12th international conference on …, 1998 - dl.acm.org
Chip-multiprocessors(CMP) are a promising approach for exploiting the increasing transistor
count on a chip. To allow sequential applications to be executed on this architecture, current …