Memory reliability will be one of the major concerns for future HPC and Exascale systems.
This concern is mostly attributed to the expected massive increase in memory capacity and …

Servers and HPC systems often use a strong memory error correction code, or ECC, to meet
their reliability and availability requirements. However, these ECCs often require significant …

Supporting error resilience in future exascale-class supercomputing systems is a critical
challenge. Due to transistor scaling trends and increasing memory density, scientific …

Proposed exascale systems will present considerable challenges. In particular, DRAM soft-
errors, or bit-flips, are expected to greatly increase due to higher memory densities and near …

Growing computer system sizes and levels of integration have made memory reliability a
primary concern, necessitating strong memory error protection. As such, large-scale systems …

The embedded memory hierarchy of microprocessors and systems-on-a-chip plays a critical
role in the overall system performance, area, power, resilience, and yield. However, as …

We present a hardware-based approach to improve the resilience of a computer system
against the errors occurred in the main memory with the help of error detecting and …

In next-generation extreme-scale systems, application performance will be limited by
memory performance characteristics. The first exascale system is projected to contain many …

High-Performance Computing (HPC) platforms become a must in automotive systems to
enable autonomous driving. However, automotive platforms must avoid Common Cause …

Fail-stop errors and Silent Data Corruptions (SDCs) are the most common failure modes for
High Performance Computing (HPC) applications. There are studies that address fail-stop …