Novel metric for load balance and congestion reducing in network on-chip

A Aroui, P Boulet, K Benhaoua, AK Singh - … Computing: Practice and …, 2020 - scpe.org
Abstract The Network-on-Chip (NoC) is an alternative pattern that is considered as an
emerging technology for distributed embedded systems. The traditional use of multi-cores in …

Simulation and performance evaluation of a network-on-chip architecture based on SystemC

TV Le-Van, XT Tran, DT Ngo - The 2012 International …, 2012 - ieeexplore.ieee.org
The Network-on-Chip (NoC) paradigm has been recently known as a competitive on-chip
communication solution for large complex systems such as multi-core and/or many-core …

ASA-routing: A-Star adaptive routing algorithm for network-on-chips

Y Cai, X Ji - Algorithms and Architectures for Parallel Processing …, 2018 - Springer
Network congestion is not an uncommon occurrence even when a routing algorithm is well-
designed, especially under the condition of a high injection rate. Moreover, it strongly affects …

A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison

K Gaffour, MK Benhaoua, AH Benyamina… - International Journal of …, 2023 - Taylor & Francis
Network on-Chip (NoC) is scalable, flexible, modular communication structure for Multi/Many-
core architectures. It allows simpler interconnect models with higher bandwidth compared to …

A study of network-on-chip performance

V Bhaskar - Proceedings of the 2021 Thirteenth International …, 2021 - dl.acm.org
Network-on-Chip (NoC) technology was introduced by incorporating the concepts of
computer networks for on-chip communication. The packet based communication has …

A novel heterogeneous congestion criterion for mesh-based networks-on-chip

R Akbar, F Safaei - Microprocessors and Microsystems, 2021 - Elsevier
In recent years, congestion in Networks-on-chip (NoC) has emerged as an important
research topic due to the increasing number of processing cores. To solve the congestion …

A novel adaptive congestion-aware and load-balanced routing algorithm in networks-on-chip

R Akbar, F Safaei, E Khodadad - Computers & Electrical Engineering, 2018 - Elsevier
Congestion-aware routing algorithms attempt to have more diversity in routes to be chosen
and avoid congested areas in networks-on-chip. In this paper, a novel fully adaptive …

Reducing bypass‐based network‐on‐chip latency using priority mechanism

AF Noghondar, M Reshadi… - IET Computers & Digital …, 2018 - Wiley Online Library
In the movement from a multi‐core to a many‐core era, cores count on the chip increases
quickly thus interconnect plays a large role in achieving the desired performance. Network …

Per-packet global congestion estimation for fast packet delivery in networks-on-chip

P Lotfi-Kamran - The Journal of Supercomputing, 2015 - Springer
Abstract Networks-on-chip (NOCs) are becoming the de facto communication fabric to
connect cores and cache banks in chip multiprocessors (CMPs). Routing algorithms, as one …

Routing pressure: A channel-related and traffic-aware metric of routing algorithm

M Tang, X Lin, M Palesi - IEEE transactions on Parallel and …, 2013 - ieeexplore.ieee.org
How to precisely measure performance of routing algorithm is an important issue when
studying routing algorithm of network-on-chip (NoC). The degree of adaptiveness is the most …