A 19.1% PAE, 22.4-dBm 53-GHz parallel power combining power amplifier with stacked-FET techniques in 90-nm CMOS
WC Sun, CN Kuo - 2019 IEEE MTT-S International Microwave …, 2019 - ieeexplore.ieee.org
A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-
nm bulk CMOS. The output stage is optimized to achieve high output power while …
nm bulk CMOS. The output stage is optimized to achieve high output power while …
Design of a 60-GHz high-output power stacked-FET power amplifier using transformer-based voltage-type power combining in 65-nm CMOS
CW Wu, YH Lin, YH Hsiao, CF Chou… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
In this paper, a 60-GHz transformer (TF)-based voltage-type-combined single-stage stacked
field-effect transistor (FET) power amplifier (PA) is demonstrated using a 65-nm CMOS …
field-effect transistor (FET) power amplifier (PA) is demonstrated using a 65-nm CMOS …
A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS
D Zhao, Y He, L Li, D Joos, W Philibert… - International Journal of …, 2011 - cambridge.org
A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal
oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based …
oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based …
A 68–79 GHz 15.6 dBm power amplifier in 65nm CMOS
W Lv, Z Duan, S Wu, Y Wang - 2018 Asia-Pacific Microwave …, 2018 - ieeexplore.ieee.org
This paper presents a 68-79 GHz fully integrated power amplifier (PA) in 65nm CMOS
technology. The PA is designed with three-stage pseudo-differential common source …
technology. The PA is designed with three-stage pseudo-differential common source …
An embedded 200 GHz power amplifier with 9.4 dBm saturated power and 19.5 dB gain in 65 nm CMOS
This paper presents a 200 GHz power amplifier in 65 nm bulk CMOS technology aiming for
maximizing the saturated power (Psat). A matched-cascode amplification cell (amp-cell) is …
maximizing the saturated power (Psat). A matched-cascode amplification cell (amp-cell) is …
A 60-GHz CMOS dual-mode power amplifier with efficiency enhancement at low output power
L Kuang, B Chi, H Jia, W Jia… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
A 60-GHz dual-mode power amplifier (PA) with efficiency enhancement at low output power
in 65-nm bulk CMOS is presented. The PA consists of two cascaded common-source driver …
in 65-nm bulk CMOS is presented. The PA consists of two cascaded common-source driver …
An adaptively biased stacked power amplifier without output matching network in 90-nm CMOS
YC Lee, TY Chen, JYC Liu - 2017 IEEE MTT-S International …, 2017 - ieeexplore.ieee.org
In this paper, a high gain high efficiency 3-stacked power amplifier (PA) without the need for
an output matching network is presented. With the transistors stacked in series, the drain …
an output matching network is presented. With the transistors stacked in series, the drain …
A 60-GHz 32-way hybrid power combination power amplifier in 55-nm bulk CMOS
L Zhang, K Ma, H Fu - IEEE Transactions on Microwave Theory …, 2022 - ieeexplore.ieee.org
This article presents a high output power-band power amplifier (PA) with 32-way power
combining in 55-nm bulk CMOS. A new hybrid power combiner (HPC) is proposed and …
combining in 55-nm bulk CMOS. A new hybrid power combiner (HPC) is proposed and …
A 21-dBm 3.7 W/mm² 28.7% PAE 64-GHz power amplifier in 22-nm FD-SOI
This letter presents the design of a 64-GHz power amplifier (PA) in a 22-nm FD-SOI CMOS
technology. Benefiting from optimized pseudodifferential cascode gain cells as well as the …
technology. Benefiting from optimized pseudodifferential cascode gain cells as well as the …
A dual-mode wideband+ 17.7-dBm 60-GHz power amplifier in 65-nm CMOS
PM Farahabadi, K Moez - IEEE Transactions on Components …, 2017 - ieeexplore.ieee.org
This paper presents a 60-GHz power amplifier (PA) utilizing a novel technique to achieve
high efficiency at high output power levels. The proposed topology provides the capability of …
high efficiency at high output power levels. The proposed topology provides the capability of …