Design Techniques for Linearity in Time-Based Analog-to-Digital Converter

M Amin, B Leung - IEEE Transactions on Circuits and Systems …, 2015 - ieeexplore.ieee.org
Due to technology scaling, the design of the conventional-type analog-to-digital converter
(ADC), which uses an operational amplifier as one of its building blocks, becomes more …

A 100-kS/s 8.3-ENOB 1.7- Time-Domain Analog-to-Digital Converter

Y Kim, C Yoo - IEEE Transactions on Circuits and Systems II …, 2014 - ieeexplore.ieee.org
A 100-kS/s time-domain analog-to-digital converter (TDADC) with successive approximation
register architecture provides 8.3 effective bits. The time-domain comparator of the TDADC …

A highly digital second-order oversampling TDC

ST Chandrasekaran, A Jayaraj… - IEEE Solid-State …, 2018 - ieeexplore.ieee.org
A second-order, single loop ΔΣ time-to-digital converter (TDC) is presented in this letter. The
proposed TDC uses two differential current-controlled oscillators as phase domain …

A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Modulator

MM Elsayed, V Dhanasekaran… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-
bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems …

Time-Interleaving Sigma–Delta Modulator-Based Digital-to-Analog Converter With Time Multiplexing in the Analog Domain

F Colodro, JM Martínez-Heredia… - … on Circuits and …, 2022 - ieeexplore.ieee.org
Sigma-delta modulator based DACs are simple circuits with low accuracy requirements in
their analog components. However, their signal bandwidth is limited by speed constrains …

A 2.4 ps resolution 2.1 mW second-order noise-shaped time-to-digital converter with 3.2 ns range in 1MHz bandwidth

B Young, S Kwon, A Elshazly… - IEEE Custom Integrated …, 2010 - ieeexplore.ieee.org
A time-to-digital converter (TDC) employs a phase-reference second-order continuous-time
delta-sigma modulator to achieve high resolution and low power. The modulator operates …

Analysis and design of an all-digital∆ Σ TDC via time-mode signal processing

F Yuan, P Parekh - IEEE Transactions on Circuits and Systems …, 2019 - ieeexplore.ieee.org
This brief presents an all-digital first-order 1-bit ΔΣ time-to-digital converter (TDC) using a
time-mode signal processing approach. Time integration is performed using a bidirectional …

A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18- CMOS

LJ Chen, SI Liu - IEEE Transactions on Very Large Scale …, 2015 - ieeexplore.ieee.org
Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-μm CMOS
process are presented. The proposed TADC uses a voltage-to-time converter (VTC) with a …

A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

KA Townsend, AR Macpherson… - Proceedings of 2010 …, 2010 - ieeexplore.ieee.org
This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter
(ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital …

A time-based bandpass ADC using time-interleaved voltage-controlled oscillators

YG Yoon, J Kim, TK Jang… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
In this paper, a bandpass analog-to-digital converter (ADC) based on time-interleaved
oversampled ADC is introduced. Unlike previous delta-sigma bandpass ADCs that require …