System-level effects of soft errors in uncore components
The effects of soft errors in processor cores have been widely studied. However, little has
been published about soft errors in uncore components, such as the memory subsystem and …
been published about soft errors in uncore components, such as the memory subsystem and …
Understanding soft errors in uncore components
The effects of soft errors in processor cores have been widely studied. However, little has
been published about soft errors in uncore components, such as memory subsystem and I/O …
been published about soft errors in uncore components, such as memory subsystem and I/O …
A framework for correction of multi-bit soft errors in L2 caches based on redundancy
K Bhattacharya, N Ranganathan… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
With the continuous decrease in the minimum feature size and increase in the chip density
due to technology scaling, on-chip L2 caches are becoming increasingly susceptible to multi …
due to technology scaling, on-chip L2 caches are becoming increasingly susceptible to multi …
Self-adaptive data caches for soft-error reliability
S Wang, J Hu, SG Ziavras - IEEE Transactions on Computer …, 2008 - ieeexplore.ieee.org
Soft-error induced reliability problems have become a major challenge in designing new
generation microprocessors. Due to the on-chip caches' dominant share in die area and …
generation microprocessors. Due to the on-chip caches' dominant share in die area and …
[PDF][PDF] Mitigating multi-bit soft errors in L1 caches using last-store prediction
Recent studies suggest that the rate of spatial multi-bit soft errors will increase with future
technology scaling. Unfortunately, multi-bit errors cannot be effectively mitigated with …
technology scaling. Unfortunately, multi-bit errors cannot be effectively mitigated with …
Robust register caching: An energy-efficient circuit-level technique to combat soft errors in embedded processors
This paper presents a cost-efficient technique to jointly use circuit-and architecture-level
techniques to protect an embedded processor's register file against soft errors. The basic …
techniques to protect an embedded processor's register file against soft errors. The basic …
Correction prediction: Reducing error correction latency for on-chip memories
The reliability of on-chip memories (eg, caches) determines their minimum operating voltage
(V min) and, therefore, the power these memories consume. A strong error correction …
(V min) and, therefore, the power these memories consume. A strong error correction …
A strategy for soft error reduction in multi core designs
R Hyman, K Bhattacharya… - 2009 IEEE International …, 2009 - ieeexplore.ieee.org
With the continuous decrease in the minimum feature size and increase in the chip density,
modern processors are being increasingly susceptible to soft errors. In the past, the …
modern processors are being increasingly susceptible to soft errors. In the past, the …
Area-efficient error protection for caches
S Kim - Proceedings of the Design Automation & Test in …, 2006 - ieeexplore.ieee.org
Due to increasing concern about various errors, current processors adopt error protection
mechanisms. Especially, protecting L2/L3 caches incur as much as 12.5% area overhead …
mechanisms. Especially, protecting L2/L3 caches incur as much as 12.5% area overhead …
Flexible cache error protection using an ECC FIFO
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection
using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of adding …
using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of adding …