Recently, run-time sleep control scheme using multiple sleep modes have been studied. In
those studies, each sleep mode has its own sleep depth. Deeper sleep mode provides …

Power Gating (PG) and Body Biasing (BB) are effective schemes to save leakage power in
standby-time. However, in run-time, their large overhead energy and latency for sleep …

The exponential increase in leakage power due to technology scaling has made power
gating an attractive design choice for low-power applications. In this paper, we explore this …

Leakage power consumption has become a major concern for VLSI circuit designers.
Leakage power will become dominant by the year 2020 as per the report of ITRS [9]. We …

This paper describes a power gating technique with multiple sleep modes where each mode
represents a trade-off between wake-up overhead and leakage savings. We show that high …

For the most recent CMOS feature sizes (eg, 90nm and 65nm), leakage power dissipation
has become an overriding concern for VLSI circuit designers. ITRS reports that leakage …

Recent studies show that peripheral circuit (including decoders, wordline drivers, input and
output drivers) constitutes a large portion of the cache leakage. In addition, as technology …

For the most recent CMOS feature sizes (eg, 90 nm and 65 nm), leakage power dissipation
has become an overriding concern for VLSI circuit designers. ITRS reports that leakage …

Leakage power dissipation becomes a dominant component in operation power in
nanometer devices. This paper describes a design methodology to implement runtime …

Today there is no need to explain the necessity of having low power dissipation devices. To
realize this objective a number of ways have been explored at various levels of design. At …