Optimum power gating sleep transistor design and implementation are critical to a
successful low-power design. This paper describes important considerations for the sleep …

Optimum sleep transistor design and implementation are critical to a successful power-
gating design. This paper describes a number of critical considerations for the sleep …

Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based
design was proposed to reduce the sleep transistor area by clustering gates to minimize the …

Power gating is one of the most effective ways to reduce leakage power. In this paper, we
introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep …

Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep
Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting …

Power gating is a circuit technique that enables high performance and low power operation.
One of the challenges in power gating is sizing the sleep transistor which is used to gate the …

Static power consumption is a major concern in nanometre technologies. Along with
technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage …

Multi-threshold CMOS is a popular circuit style that will provide high performance and low
power operation. Optimally sizing the gating sleep transistor to provide adequate …

Multithreshold CMOS (MTCMOS) technology has become a popular technique for standby
power reduction. Sleep transistor insertion in circuits is an effective application of MTCMOS …

Power gating is one of the most effective techniques in reducing the standby leakage current
of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizing which …