Heterogeneous Technology Integration

J Kim, EP Gousev, MM Nowak - US Patent App. 12/731,520, 2011 - Google Patents
BACKGROUND 0002 Integrated circuits can be designed using different technologies, for
example complementary metal oxide semi conductor (CMOS) technology, glass technology …

Packaging mechanisms for dies with different sizes of connectors

CH Chen, CS Chen, CW Hsiao - US Patent 9,646,894, 2017 - Google Patents
BACKGROUND Semiconductor devices are used in a variety of electronic applications, such
as personal computers, cell phones, digi tal cameras, and other electronic equipment, as …

Skew compensation for a stacked die

KS Abugharbieh, DJ Ferris III, L Jones… - US Patent …, 2015 - Google Patents
BACKGROUND Stacked die ICs may be formed from different interposer dies (“interposers').
These interposers may have different sizes and accommodate different types and/or …

Hybrid technology 3-d die stacking

A Sarkar, RV Mahajan - US Patent App. 15/774,512, 2020 - Google Patents
BACKGROUND [0002] In the fabrication of electronic apparatuses, the stacking of multiple
dies has become popular because of advantages in reducing the physical space of a …

Dual-side interconnected CMOS for stacked integrated circuits

A Chandrasekaran, B Henderson - US Patent 8,525,342, 2013 - Google Patents
BACKGROUND Stacked ICs increase device functionality and decrease occupied area by
stacking dies vertically. In stacked ICs, a second die is stacked on a first die allowing …

Device and method of very high density routing used with embedded multi-die interconnect bridge

RA May, WLK Jen, JL Rosch, IA Salama… - US Patent App. 17 …, 2022 - Google Patents
BACKGROUND [0003] The electronics industry has continued to face an ever-increasing
demand for faster and more powerful pro cessing capacity, as well as increased storage …

Multi-chip wafer level package

CH Yu, CH Tung, TL Shao, CH Yu, DY Shih - US Patent 8,754,514, 2014 - Google Patents
BACKGROUND Since the invention of the integrated circuit, the semicon ductor industry has
experienced rapid growth due to continu ous improvements in the integration density of a …

Die backside wire bond technology for single or stacked die package

S Periaman, KC Ooi, BE Cheah, YH Chew - US Patent 8,198,716, 2012 - Google Patents
BACKGROUND The present disclosure generally relates to the field of electronics. More
particularly, an embodiment of the inven tion relates to die backside wire bond technology. A …

Testing die-to-die bonding and rework

A Rahman - US Patent 8,648,615, 2014 - Google Patents
BACKGROUND The probability that a flaw will occur in a die when manu facturing an
integrated circuit (IC) generally increases as the size of the die used to implement the IC …

Jigs with controlled spacing for bonding dies onto package substrates

YL Hsiao, CH Yu, CS Liu, CL Hwang - US Patent 8,373,269, 2013 - Google Patents
BACKGROUND In the packaging of integrated circuits, dies may be pack aged onto a
package Substrate (sometimes referred to as a laminate Substrate), which includes metal …