Improving energy efficiency by making DRAM less randomly accessed
Existing techniques manage power for the main memory by passively monitoring the
memory traffic, and based on which, predict when to power down and into which low-power …
memory traffic, and based on which, predict when to power down and into which low-power …
Rethinking DRAM power modes for energy proportionality
KT Malladi, I Shaeffer, L Gopalakrishnan… - 2012 45th Annual …, 2012 - ieeexplore.ieee.org
We re-think DRAM power modes by modeling and characterizing inter-arrival times for
memory requests to determine the properties an ideal power mode should have. This …
memory requests to determine the properties an ideal power mode should have. This …
Delay-hiding energy management mechanisms for dram
Current trends in data-intensive applications increase the demand for larger physical
memory, resulting in the memory subsystem consuming a significant portion of system's …
memory, resulting in the memory subsystem consuming a significant portion of system's …
A comprehensive approach to DRAM power management
This paper describes a comprehensive approach for using the memory controller to improve
DRAM energy efficiency and manage DRAM power. We make three contributions:(1) we …
DRAM energy efficiency and manage DRAM power. We make three contributions:(1) we …
Partial row activation for low-power dram system
Owing to increasing demand of faster and larger DRAM system, the DRAM system accounts
for a large portion of the total power consumption of computing systems. As memory traffic …
for a large portion of the total power consumption of computing systems. As memory traffic …
Scheduler-based DRAM energy management
V Delaluz, A Sivasubramaniam, M Kandemir… - Proceedings of the 39th …, 2002 - dl.acm.org
Previous work on DRAM power-mode management focused on hardware-based techniques
and compiler-directed schemes to explicitly transition unused memory modules to low …
and compiler-directed schemes to explicitly transition unused memory modules to low …
Memory controller policies for DRAM power management
X Fan, C Ellis, A Lebeck - … of the 2001 international symposium on Low …, 2001 - dl.acm.org
The increasing importance of energy efficiency has produced a multitude of hardware
devices with various power management features. This paper investigates memory …
devices with various power management features. This paper investigates memory …
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
AM Amin, ZA Chishti - Proceedings of the 16th ACM/IEEE international …, 2010 - dl.acm.org
DRAM power and energy efficiency considerations are becoming increasingly important for
low-power and mobile systems. Using lower power modes provided by commodity DRAM …
low-power and mobile systems. Using lower power modes provided by commodity DRAM …
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
The widespread use of multicore processors has dramatically increased the demand on
high memory bandwidth and large memory capacity. As DRAM subsystem designs stretch to …
high memory bandwidth and large memory capacity. As DRAM subsystem designs stretch to …
Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs
DRAMs require periodic refresh for preserving data stored in them. The refresh interval for
DRAMs depends on the vendor and the design technology they use. For each refresh in a …
DRAMs depends on the vendor and the design technology they use. For each refresh in a …