3D DRAM design and application to 3D multicore systems

H Sun, J Liu, RS Anigundi, N Zheng… - IEEE Design & Test …, 2009 - ieeexplore.ieee.org
Editor's note: From a system architecture perspective, 3D technology can satisfy the high
memory bandwidth demands that future multicore/manycore architectures require. This …

Design of 3D DRAM and its application in 3D integrated multi-core computing systems

H Sun, J Liu, R Anigundi, N Zheng, J Lu… - IEEE Design and …, 2009 - ieeexplore.ieee.org
This paper concerns appropriate 3D DRAM architecture design and the potential of using
3D DRAM to implement both L2 cache and main memory in 3D multi-core processor-DRAM …

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

K Chen, S Li, N Muralimanohar, JH Ahn… - … , Automation & Test …, 2012 - ieeexplore.ieee.org
Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future
memory architectures to satisfy the ever-increasing demands on performance, power, and …

Design space exploration for 3D-stacked DRAMs

C Weis, N Wehn, L Igor, L Benini - 2011 Design, Automation & …, 2011 - ieeexplore.ieee.org
3D integration based on TSV (through silicon via) technology enables stacking of multiple
memory layers and has the advantage of higher bandwidth at lower energy consumption for …

3-D WiRED: A novel wide I/O DRAM with energy-efficient 3-D bank organization

I Thakkar, S Pasricha - IEEE Design & Test, 2015 - ieeexplore.ieee.org
WIDE I/O DRAM is a promising 3-D memory architecture for low-power/highperformance
computing. This paper proposes a new WIDE I/O DRAM architecture to reduce access …

Heterogeneous memory management for 3D-DRAM and external DRAM with QoS

LN Tran, FJ Kurdahi, AM Eltawil… - 2013 18th Asia and …, 2013 - ieeexplore.ieee.org
This paper presents an innovative memory management approach to utilize both 3D-DRAM
and external DRAM (ex-DRAM). Our approach dynamically allocates and relocates memory …

Architecture design exploration of three-dimensional (3D) integrated DRAM

R Anigundi, H Sun, JQ Lu, K Rose… - 2009 10th International …, 2009 - ieeexplore.ieee.org
Motivated by increasingly promising three-dimensional (3D) integration technologies, this
paper reports an architecture design of 3D integrated dynamic RAM (DRAM). To …

A 3D SoC design for H. 264 application with on-chip DRAM stacking

T Zhang, K Wang, Y Feng, Y Chen, Q Li… - 2010 IEEE …, 2010 - ieeexplore.ieee.org
Three-dimensional (3D) on-chip memory stacking has been proposed as a promising
solution to the “memory wall” challenge with the benefits of low access latency, high data …

An efficient distributed memory interface for many-core platform with 3D stacked DRAM

I Loi, L Benini - 2010 Design, Automation & Test in Europe …, 2010 - ieeexplore.ieee.org
Historically, processor performance has increased at a much faster rate than that of main
memory and up-coming NoC-based many-core architectures are further tightening the …

Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy

GH Loh - Proceedings of the 42nd Annual IEEE/ACM …, 2009 - dl.acm.org
3D-integration is a promising technology to help combat the" Memory Wall" in future multi-
core processors. Past work has considered using 3D-stacked DRAM as a large last-level …