ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars

A Shafiee, A Nag, N Muralimanohar… - ACM SIGARCH …, 2016 - dl.acm.org
A number of recent efforts have attempted to design accelerators for popular machine
learning algorithms, such as those involving convolutional and deep neural networks (CNNs …

Newton: Gravitating towards the physical limits of crossbar acceleration

A Nag, R Balasubramonian, V Srikumar, R Walker… - IEEE Micro, 2018 - ieeexplore.ieee.org
Many recent works take advantage of highly parallel analog in-situ computation in memristor
crossbars to accelerate the many vector-matrix multiplication operations in deep neural …

PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference

A Ankit, IE Hajj, SR Chalamalasetti, G Ndu… - Proceedings of the …, 2019 - dl.acm.org
Memristor crossbars are circuits capable of performing analog matrix-vector multiplications,
overcoming the fundamental energy efficiency limitations of digital logic. They have been …

Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication

M Hu, JP Strachan, Z Li, EM Grafals, N Davila… - Proceedings of the 53rd …, 2016 - dl.acm.org
Vector-matrix multiplication dominates the computation time and energy for many workloads,
particularly neural network algorithms and linear transforms (eg, the Discrete Fourier …

Making memristive neural network accelerators reliable

B Feinberg, S Wang, E Ipek - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Deep neural networks (DNNs) have attracted substantial interest in recent years due to their
superior performance on many classification and regression tasks as compared to other …

Multiply accumulate operations in memristor crossbar arrays for analog computing

J Chen, J Li, Y Li, X Miao - Journal of Semiconductors, 2021 - iopscience.iop.org
Memristors are now becoming a prominent candidate to serve as the building blocks of non-
von Neumann in-memory computing architectures. By mapping analog numerical matrices …

Vesti: Energy-efficient in-memory computing accelerator for deep neural networks

S Yin, Z Jiang, M Kim, T Gupta… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
To enable essential deep learning computation on energy-constrained hardware platforms,
including mobile, wearable, and Internet of Things (IoT) devices, a number of digital ASIC …

Analog weights in ReRAM DNN accelerators

JK Eshraghian, SM Kang, S Baek… - … Circuits and Systems …, 2019 - ieeexplore.ieee.org
Artificial neural networks have become ubiquitous in modern life, which has triggered the
emergence of a new class of application specific integrated circuits for their acceleration …

Memristor‐based analog computation and neural network classification with a dot product engine

M Hu, CE Graves, C Li, Y Li, N Ge… - Advanced …, 2018 - Wiley Online Library
Using memristor crossbar arrays to accelerate computations is a promising approach to
efficiently implement algorithms in deep neural networks. Early demonstrations, however …

Colonnade: A reconfigurable SRAM-based digital bit-serial compute-in-memory macro for processing neural networks

H Kim, T Yoo, TTH Kim, B Kim - IEEE Journal of Solid-State …, 2021 - ieeexplore.ieee.org
This article (Colonnade) presents a fully digital bit-serial compute-in-memory (CIM) macro.
The digital CIM macro is designed for processing neural networks with reconfigurable 1-16 …