Recent research shows that the occupancy of the coherence controllers is a major
performance bottleneck for distributed cache coherent shared memory multiprocessors. A …

Recent research shows that the occupancy of the coherence controllers is a major
performance bottleneck for distributed cache coherent shared memory multiprocessors. In …

In Cache Only Memory Architecture (COMA) for distributed shared memory multiprocessors,
the physical location of a datum is completely decoupled from its address by organizing the …

Application specific coherence control for high performance distributed shared memory |
Papers from the symposium on Experiences with distributed and multiprocessor systems skip …

Appropriate solution of the well-known cache coherence problem in shared memory
multiprocessors is one of the key issues in improving the performance and scalability of …

Bus-based shared-memory multiprocessors with coherent caches have recently become
very popular. To achieve high performance, these systems rely on increasingly sophisticated …

This paper presents a singly-linked distributed directory (SDD) cache coherence protocol
and compares the performance of the SDD protocol with the fully mapped centralized …

The authors describe and analyze two algorithms for maintaining cache coherence in
multiprocessor systems with parallel communication channels and many processors. A …

Shared memory multiprocessors play an increasingly important role in enterprise and
scientific computing facilities. Remote misses limit the performance of shared memory …

We present a new arrangement of directory bits called the segment directory to improve
directory storage efficiency: a segment directory can point to several sharing processors with …