Area and test time are two major overheads encountered during data path synthesis for
BIST. This paper presents an attempt towards testability enhancement in data path BIST …

This paper presents an attempt towards design quality improvement by incorporating of self-
testability features during data path (high-level) synthesis. This method is based on the use …

Existing high-level BIST synthesis methods focus on one objective, minimizing either area
overhead or test time. Hence, those methods do not render exploration of large design …

The purpose of this work is to develop a test synthesis technique based on BIST
methodology which uses the test metrics (ie controllability and observability) obtained by test …

Datapath architectures are widely used in today's complex integrated circuits, such as
commercial microprocessors or specialized digital signal processors. A very effective BIST …

Multifunction arithmetic logic units (ALUs) that realize complex arithmetic and logic
operations (like the operations of the 74/spl times/181 family) are widely used in today's …

Power dissipation during test application is an emerging problem due to yield and reliability
concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs …

Test Structure Verification (TSV) is the process used to assess the conformance of a circuit to
a set of predefine Design For Testability (DFT) rules. Test generation algorithms are typically …

BIST Testability Enhancement Using High Level Test Synthesis For Behavioral And Structural
Designs - Test Symposium, 1997. (ATS Page 1 BIST Testability Enhancement Using High …

We propose simple modifications to existing BIST schemes. These modifications
significantly improve the path delay fault coverage. For example, a modified circular self-test …