Improved parallelization of legacy embedded software on soft-core MPSoCs through automatic loop transformations

K Heid, J Wenzel, C Hochberger - FSP Workshop 2018; Fifth …, 2018 - ieeexplore.ieee.org
Today, a growing number of digital systems containing a software part is realized on Field
Programmable Gate Arrays. This allows to use application specific multi-core architectures …

Symbolic multi-level loop mapping of loop programs for massively parallel processor arrays

A Tanase, M Witterauf, J Teich, F Hannig - ACM Transactions on …, 2017 - dl.acm.org
Today's MPSoCs (multiprocessor systems-on-chip) have brought up massively parallel
processor array accelerators that may achieve a high computational efficiency by exploiting …

OCA–Code Advisory Tool for OpenMP Parallelization of Sequential Code

G Haber, S Altman, Y Ben-Asher… - 2023 IEEE 16th …, 2023 - ieeexplore.ieee.org
Programming multicore embedded systems is a real challenge and is often realized using
OpenMP that is used to parallelize sequential code Unfortunately, auto-parallelizers and …

Automatic mapping of nested loops to FPGAs

U Bondhugula, J Ramanujam… - Proceedings of the 12th …, 2007 - dl.acm.org
This paper present a framework for automatic mapping of perfectly nested loops with
constant dependences onto regular processor arrays, suitable for direct implementation on …

Generating Optimized FPGA Based MPSoCs to Parallelize Legacy Embedded Software with Customizable Throughput

K Heid, C Hochberger - 2020 - dl.gi.de
Executing legacy software on newly developed systems can lead to problems regarding the
required throughput of the software. Automatic software parallelization can help to achieve a …

Challenges in exploitation of loop parallelism in embedded applications

A Kejariwal, AV Veidenbaum, A Nicolau… - Proceedings of the 4th …, 2006 - dl.acm.org
Embedded processors have been increasingly exploiting hardware parallelism. Vector units,
multiple processors or cores, hyper-threading, special-purpose accelerators such as DSPs …

Autostreams: Fully automatic parallelization of legacy embedded applications with soft-core mpsocs

K Heid, C Hochberger - 2018 International Conference on …, 2018 - ieeexplore.ieee.org
In many digital systems a considerable part of the functionality is defined in software.
Implementing these systems on Field Programmable Gate Arrays offers the additional …

Automatic loop parallelization via compiler guided refactoring

P Larsen, R Ladelsky, J Lidman, SA McKee, S Karlsson… - 2011 - orbit.dtu.dk
For many parallel applications, performance relies not on instruction-level parallelism, but
on loop-level parallelism. Unfortunately, many modern applications are written in ways that …

A compiler framework for automatically mapping data parallel programs to heterogeneous MPSoCs

K Chandramohan, MFP O'Boyle - Proceedings of the 2014 International …, 2014 - dl.acm.org
Many of today's embedded devices are based on MultiProcessor System-on-Chips
(MPSoCs). Such devices are usually heterogeneous, containing DSPs and specialized …

Automatic generation of application-specific accelerators for fpgas from python loop nests

D Sheffield, M Anderson… - … Conference on Field …, 2012 - ieeexplore.ieee.org
We present Three Fingered Jack, a highly productive approach to mapping vectorizable
applications to the FPGA. Our system applies traditional dependence analysis and …