A processor comprising a mode indicator, a plurality of processing cores, and a neural
network unit (NNU), comprising a memory array, an array of neural processing units (NPU) …

A processor comprises a neural network unit (NNU) and a processing complex (PC)
comprising a processing core and cache memory. The NNU comprises neural processing …

A processor comprising a plurality of processing cores, a last level cache memory (LLC)
shared by the plurality of processing cores, and a neural network unit (NNU) comprising an …

(57) ABSTRACT A processor has an instruction fetch unit that fetches ISA instructions from
memory and execution units that perform operations on instruction operands to generate …

(57) ABSTRACT A processor includes a front-end portion that issues instruc-tions to
execution units that execute the issued instructions. A hardware neural network unit (NNU) …

A microprocessor includes an indicator and a plurality of processing cores. Each of the
plurality of processing cores is configured to sample the indicator. When the indicator …

The present disclosure relates to a processor for implement ing artificial neural networks, for
example, convolutional neural networks. The processor includes a memory control ler …

A processor having a dependency matrix comprises a first array comprising a plurality of first
cells. A second array couples to the first array and comprises a plurality of second cells. A …

A processor includes a processor core and a calculation cir cuit. The processor core
includes logic determine a set of weights for use in a convolutional neural network (CNN) …

The present disclosure relates to a processor for implementing artificial neural networks, for
example, convolutional neural networks. The processor includes a memory controller group …