(57) ABSTRACT A processor includes a front-end portion that issues instruc-tions to
execution units that execute the issued instructions. A hardware neural network unit (NNU) …

(57) ABSTRACT A processor has an instruction fetch unit that fetches ISA instructions from
memory and execution units that perform operations on instruction operands to generate …

A processor comprising a mode indicator, a plurality of processing cores, and a neural
network unit (NNU), comprising a memory array, an array of neural processing units (NPU) …

According to a first aspect of the invention, a pipelined hardware implementation of a neural
network circuit is provided. The inventive neural network circuit includes an input Stage for …

At least one neural network accelerator performs operations of a first subset of layers of a
neural network on an input data set, generates an intermediate data set, and stores the inter …

A circuit for performing neural network computations for a neural network comprising a
plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of …

A heterogeneous processor architecture for integrating a convolutional neural network
(CNN) and a recurrent neural network (RNN) into a single high-performance, low-power …

(57) ABSTRACT A dynamically adaptive neural network processing system includes
memory to store instructions representing a neural network in contiguous blocks, hardware …

A processing unit for neural network processing includes: an instruction memory that stores
tasks including one or more instructions; a data memory that stores data related to the tasks; …

The present disclosure relates to a processor for implement ing artificial neural networks, for
example, convolutional neural networks. The processor includes a memory control ler …