Single poly non-volatile memory having a PMOS write path and an NMOS read path
GC Chern - US Patent 6,166,954, 2000 - Google Patents
A single-poly, floating gate memory cell includes a PMOS write and an NMOS read path.
The memory cell's write path includes a PMOS half-transistor coupled in series with a PMOS …
The memory cell's write path includes a PMOS half-transistor coupled in series with a PMOS …
PMOS single-poly non-volatile memory structure
SDT Chang - US Patent 5,761,121, 1998 - Google Patents
A P-channel single-poly non-volatile memory cell having P+ source and P+ drain regions
and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon …
and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon …
Single poly NVM devices and arrays
W Chen, RJ De Souza, X Lin, PM Parris - US Patent 8,344,443, 2013 - Google Patents
A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a
select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well …
select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well …
Nonvolatile memory solution using single-poly pFlash technology
A Wang, ST Chang, HC Lin, TH Shiau, IS Liu… - US Patent …, 2006 - Google Patents
(57) ABSTRACT A single-poly two-transistor PMOS memory cell for mul tiple-time
programming applications includes a PMOS floating gate transistor sharing a drain/source …
programming applications includes a PMOS floating gate transistor sharing a drain/source …
Single poly non-volatile memory
HM Chen, SC Wang, HP Tsai - US Patent 7,209,392, 2007 - Google Patents
52) US C 365/185.26: 365/185.28 formed between its source and drain; and a second
floating (52) irr r eaf Vs gate transistor having a drain, a source coupled to the drain (58) …
floating (52) irr r eaf Vs gate transistor having a drain, a source coupled to the drain (58) …
PMOS memory array having OR gate architecture
SDT Chang, CD Nguyen, GS Yuen… - US Patent 5,909,392, 1999 - Google Patents
A nonvolatile PMOS memory array includes a plurality of pages, where each column of a
page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS …
page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS …
Single-poly nonvolatile memory cell
YH Li, YH Lai, MS Lo, SC Huang - US Patent 9,640,259, 2017 - Google Patents
PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS
floating gate transistor com prises a floating gate and a gate oxide layer between the floating …
floating gate transistor com prises a floating gate and a gate oxide layer between the floating …
Asymmetric single poly NMOS non-volatile memory cell
Y Roizin, E Pikhay, I Naveh - US Patent 7,800,156, 2010 - Google Patents
5,051,951 A 9/1991 Maly et al. 5,188.976 A 2f1993 Kume et al. 5,354,703 A 10, 1994 G11
5,455,789 A 10, 1995 Nakamura et al. 5,646,430 A 7/1997 Kaya et al. 5,687,115 A* 1 …
5,455,789 A 10, 1995 Nakamura et al. 5,646,430 A 7/1997 Kaya et al. 5,687,115 A* 1 …
Non-volatile memory device
HM Chen, HM Lee, SJ Shen, CH Hsu - US Patent 7,250,654, 2007 - Google Patents
A single-poly non-volatile memory device invented to integrate into logic process is
disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS …
disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS …
Multibit-per-cell non-volatile memory with error detection and correction
HC So, SC Wong - US Patent 5,909,449, 1999 - Google Patents
BACKGROUND 1. Field of the Invention This invention relates to non-volatile Semiconductor
memory and more Specifically to circuits and methods for detecting and correcting data …
memory and more Specifically to circuits and methods for detecting and correcting data …