Digital equalization with ADC-based receivers: Two important roles played by digital signal processingin designing analog-to-digital-converter-based wireline …

S Kiran, S Cai, Y Zhu, S Hoyos… - IEEE Microwave …, 2019 - ieeexplore.ieee.org
Wireline input/output (I/O) bandwidth demand within networks in large data centers has
increased rapidly over the last decade because of the explosion in data generation from …

[图书][B] Analog-to-digital converters for high-speed links

V Abramzon - 2008 - search.proquest.com
In today's technology, high-speed links play an important role, enabling faster, cheaper, and
more reliable data communications. Data converters, present in some form in almost all …

Analog-to-digital converter-based serial links: An overview

S Palermo, S Hoyos, S Cai, S Kiran… - IEEE Solid-State Circuits …, 2018 - ieeexplore.ieee.org
The ever-increasing number of networked devices and cloud computing applications has
created dramatic growth in data center traffic. This necessitates that the serial links that …

CMOS ADC-based receivers for high-speed electrical and optical links

S Palermo, S Hoyos, A Shafik… - IEEE …, 2016 - ieeexplore.ieee.org
CMOS ADC-based serial link receivers enable powerful digital equalization and symbol
detection techniques for high data rate operation over electrical and optical wireline …

[图书][B] System-driven circuit design for ADC-based wireline data links

K Zheng - 2018 - search.proquest.com
In the era of connectivity, wireline I/O has been a key technology underpinning the
aggressive performance improvements of computer and communication systems. All …

A 1.41 pJ/b 224Gb/s PAM-4 SerDes receiver with 31dB loss compensation

Y Segal, A Laufer, A Khairi, Y Krupnik… - … Solid-State Circuits …, 2022 - ieeexplore.ieee.org
The emergence of cloud computing, machine learning, and artificial intelligence is gradually
saturating network workloads, necessitating rapid growth in datacenter bandwidth, which …

A 6-bit 1.5-GS/s SAR ADC with smart speculative two-tap embedded DFE in 130-nm CMOS for wireline receiver applications

A Mahmoudi, P Torkzadeh… - IEEE Transactions on Very …, 2021 - ieeexplore.ieee.org
Implementing wireline receivers with a front-end analog-to-digital converter (ADC) allows for
complex, flexible, and robust signal processing algorithms in the digital domain, as well as …

3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS

A Shafik, EZ Tabasy, S Cai, K Lee… - … Solid-State Circuits …, 2015 - ieeexplore.ieee.org
ADC-based receivers are currently being proposed in high-speed serial link applications to
enable flexible, complex, and robust digital equalization in order to support operation over …

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI

S Rylov, T Beukema, Z Toprak-Deniz… - … Solid-State Circuits …, 2016 - ieeexplore.ieee.org
As CMOS devices continue to scale down in voltage and area, digital-based high-speed
serial I/Os [1] become increasingly competitive with analog-based designs [2, 3]. In addition …

Design considerations and performance trade-offs for 56Gb/s discrete multi-tone electrical link

G Kim, W Kwon, T Toifl, Y Leblebici… - 2019 IEEE 62nd …, 2019 - ieeexplore.ieee.org
For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-
based receiver (RX) has become a dominant architecture due to its strong equalization …