A 0.84 ps-LSB 2.47 mW time-to-digital converter using charge pump and SAR-ADC

Z Xu, S Lee, M Miyahara… - Proceedings of the IEEE …, 2013 - ieeexplore.ieee.org
We propose a time-to-digital converter (TDC) using a charge pump and a SAR-ADC. With
this architecture, high time resolution is attainable by increasing the charging current or …

A 1 ps-resolution integrator-based time-to-digital converter using a sar-adc in 90nm cmos

Z Xu, M Miyahara, A Matsuzawa - 2013 IEEE 11th International …, 2013 - ieeexplore.ieee.org
We propose a time-to-digital converter (TDC) that uses a G mC integrator to translate the
time interval into voltage, and quantizes this voltage with a SAR-ADC. The proposed method …

A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

KA Townsend, AR Macpherson… - Proceedings of 2010 …, 2010 - ieeexplore.ieee.org
This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter
(ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital …

A low power TDC with 0.5 ps resolution for ADPLL in 40nm CMOS

X Liu, L Ma, J Xiang, N Yan, H Xie… - 2015 IEEE 11th …, 2015 - ieeexplore.ieee.org
A low power time-to-digital converter (TDC) with high resolution is presented in this paper.
The TDC employs a digital-to-time converter (DTC) to reduce the dynamic range based on a …

A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register

KS Kim, WS Yu, SH Cho - IEEE Journal of Solid-State Circuits, 2014 - ieeexplore.ieee.org
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For
pipelined operation, a novel time-register is proposed which is capable of storing, adding …

A 1.7 mW 11b 1–1–1 MASH ΔΣ time-to-digital converter

Y Cao, P Leroux, W De Cock… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
Recently, high-resolution TDCs have gained more and more popularity due to their
increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight …

A hybrid time-to-digital converter based on residual time extraction and amplification

J Wu, W Zhang, X Yu, Q Jiang, L Zheng, W Sun - Microelectronics Journal, 2017 - Elsevier
This paper presents a novel hybrid time-to-digital converter (TDC) for high resolution and
wide range time measurement, where a two-stage TDC cooperates with a two-step TDC …

A 71dB dynamic range third-order ΔΣ TDC using charge-pump

M Gande, N Maghari, T Oh… - 2012 Symposium on VLSI …, 2012 - ieeexplore.ieee.org
A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture
combines the principles of noise-shaping quantization and charge-pump to build a third …

A hybrid-domain two-step time-to-digital converter using a switch-based time-to-voltage converter and SAR ADC

J Kim, YH Kim, KS Kim, W Yu… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
In this brief, an energy-efficient time-to-digital converter (TDC) using a hybrid of time-and
voltage-domain circuits is presented. The proposed TDC operates in two steps, ie, first in the …

A 2.3-mW, 950-MHz, 8-bit fully-time-based subranging ADC using highly-linear dynamic VTC

K Ohhata - 2018 IEEE Symposium on VLSI Circuits, 2018 - ieeexplore.ieee.org
A novel fully-time-based subranging analog-to-digital converter (ADC) is proposed. Two
time-based ADCs (TB ADCs) are used for both coarse and fine ADCs, resulting in low power …