GG Henry, T Parks - US Patent 10,409,767, 2019 - Google Patents
An array of N processing units (PU) each has: an accumulator; an arithmetic unit performs an operation on first, second and third inputs to generate a result to store in the accumulator …
GG Henry, KC Houck - US Patent 10,395,165, 2019 - Google Patents
N processing units (PU) each have an arithmetic unit (AU) that performs an operation on first, second and third inputs to generate a result to store in an accumulator having an output …
GG Henry, T Parks - US Patent 10,366,050, 2019 - Google Patents
A neural network unit (NNU) includes N neural processing units (NPU). Each NPU has an arithmetic unit and an accumulator. First and second multiplexed registers of the N NPUs …
GG Henry, T Parks - US Patent 10,380,064, 2019 - Google Patents
A neural network unit including a register programmable with a representation of a reciprocal value of a divisor and a plurality of neural processing units (NPU). Each NPU has …
GG Henry, T Parks - US Patent 10,509,765, 2019 - Google Patents
(57) ABSTRACT A neural network unit includes a programmable indicator, a first memory that holds first operands, a second memory that holds second operands, neural processing …
GG Henry, T Parks - US Patent 10,387,366, 2019 - Google Patents
A neural network unit includes first and second memories that hold rows of respective N weight and data words and provides a row of them to N corresponding neural processing …
GG Henry, T Parks, KT O'brien - US Patent 10,671,564, 2020 - Google Patents
A neural network unit has a first memory that holds elements of a data matrix and a second memory that holds elements of a convolution kernel. An array of neural processing units …
GG Henry, KC Houck, P Palangpour - US Patent 10,140,574, 2018 - Google Patents
First/second memories hold rows of N weight/data words. The first memory address has log2 W bits and an extra bit. Each of N processing units (PU) of index J has first and second …
GG Henry, T Parks - US Patent 10,776,690, 2020 - Google Patents
A neural network unit includes a register programmable with a control value, a plurality of neural processing units (NPU), and a plurality of activation function units (AFU). Each NPU …