Numerical Analysis on Power Semiconductor Die Passivation Layer Stack Structure Behavior

Z Zhou, H Fan - 2022 23rd International Conference on …, 2022 - ieeexplore.ieee.org
… portion of material atop stack layer is lower than layer stack structure, its lower shape center
… due to its shape center is higher than layer stack structure. In that case, the overall package …

Study on the characteristics of Zn-based oxide semiconductor and its 3D stacked device for flash memory applications

김언기 - 2015 - s-space.snu.ac.kr
devices. Therefore, it is very important to establish a concrete understanding of the device
… Furthermore, to be implemented in novel devices applications, various device structures

Increasing trapped carrier density in nanoscale GeSeAs Films by As ion Implantation for selector devices in 3D-Stacking Memory

G Liu, T Li, L Wu, Y Chen, B Liu, Z Ma… - ACS Applied Nano …, 2019 - ACS Publications
… T-shaped device structure with a 190 nm diameter and 600 nm height W electrode was …
The electrical characteristics of the selector devices were tested using a semiconductor device

Doping–Dedoping Interplay to Realize Patterned/Stacked All-Polymer Optoelectronic Devices

J Kim, M Kang, J Cho, SH Yu… - ACS applied materials & …, 2019 - ACS Publications
… method is the ability to fabricate multilayer polymer semiconductor devices, while
preserving each polymer’s own morphological/structural characteristics. For this purpose, we …

A source/drain-on-insulator structure to improve the performance of stacked nanosheet field-effect transistors

V Jegadheesan, K Sivasankaran - Journal of Computational Electronics, 2020 - Springer
… to ensure accurate prediction of the subthreshold characteristics of the device. As the stacked
channel structure involves different scattering mechanisms (surface roughness, phonon, …

Novel SONOS–type nonvolatile memory device with stacked tunneling and charge trapping layers

PH Tsai, KS Chang-Liao, TY Wu, TK Wang… - Solid-state …, 2008 - Elsevier
semiconductor memory (NVM) devices with stacked tunneling … of NVM device were achieved
by adopting stacked tunneling … was observed for device with stacked charge trapping layer. …

Interlayer orientation-dependent light absorption and emission in monolayer semiconductor stacks

H Heo, JH Sung, S Cha, BG Jang, JY Kim, G Jin… - Nature …, 2015 - nature.com
… Random bilayer stacks were fabricated by manual stacking of individual MoS 2 and WS 2
MLs; thus the rotation-misfit order is unknown. Heteroepitaxial stacking growth, in which the …

Performance evaluation of stacked gate oxide/high K spacers based gate all around device architectures at 10 nm technology node

MS Narula, A Pandey - Silicon, 2022 - Springer
… arising due to scaling down of devices, a paradigm shift is occurring … semiconductor devices
are becoming primary choice for future CMOS technology. Multigate semiconductor devices

3-D stacked synapse array based on charge-trap flash memory for implementation of deep neural networks

YJ Park, HT Kwon, B Kim, WJ Lee… - … on Electron Devices, 2018 - ieeexplore.ieee.org
… a 3-D stacked synapse array and present the structure, operation, and … Korea Semiconductor
Research Consortium support program for the development of future semiconductor devices

Design for variation-immunity in sub-10-nm stacked-nanowire FETs to suppress LER-induced random variations

J Park, H Lee, S Oh, C Shin - … Transactions on Electron Devices, 2016 - ieeexplore.ieee.org
structure—the inserted-oxide FinFET (iFinFET)—has been proposed [3]. A GAA FET structure
is currently one of the promising device structures that … by the Future Semiconductor Device