… architectural parameters considering architecting STT-RAM/SRAM hybrid cache to a VLIW
processor. It costs 1 cycle and 3 cycles to read from and write to STT-RAM respectively, and 1 …

… or interleaved access pattern in STT-RAM-based hybrid memory. However, the overall ef…
cussed for a VLIW processor equipped with modern STTRAM-based hybrid memory. This paper …

… VLIW processor before; the first addresses the problem of increased robustness to memory/…
coherency protocol for an embedded VLIW multimedia processor that keeps into account as …

… is relatively simple, consisting of a set of functional units, registers, and paths to memory. …
HP chose the ST-231 VLIW CPU because it performed uniformly well across all of the …

… The ISA is loosely modeled on the ISA of the HP/ST Lx (ST200) family of VLIW embedded
… fetches a VLIW instruction from the attached instruction memory, and splits it into syllables …

… VLIW processor such as the number and type of functional units (FUs), supported instructions,
memory-… The VEX ISA is loosely modeled on the ISA of HP/ST Lx (ST200) family of VLIW …

… If the instruction is a memory write operation, we save also the content of the accessed memory
… We also include two static approaches: St-bb, limited to basic blocks and St-ts, with the …

… VEX ISA represents a subset of the HP/ST Lx (ST200) family … the memory subsystem and
any instruction-memory configuration could be used including a scratchpad instruction memory …

… /ST Lx [5] VLIW family. The VEX C compiler [21] used in this study is a derivation of HP/ST …
done for a perfect memory model with no cache misses and for a real memory model (64KB, …

… The CPU contains two data units for memory and simple ALU … memory is introduced to
reduce the overhead of the true dual-port memory used in CPU configurations with two LD/ST …