… Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop,
using VLSI technology. The designed counter can be used in the divider chip of the phase …

… The first is the buffered static logic latched by static master slave D flipflops. The … VLSI
chips in this paper. The method makes it possible to estimate the power consumption of a chip …

… In the near-future logic VLSI systems, data stored in the FFs will … To evaluate radiation
hardness of the chips precisely, we … , at each FF in the chips. It is desired to examine all FFs in the …

… distributing it to all the flip-flops throughout the chip. This paper introduces novel flip-flops
to overcome the drawbacks of the conventional flip-flops described above [11]. One proposed …

… The design of the clocking subsystem represents a crucial aspect in CMOS VLSI integrated
circuits, as it strongly affects not only the chip performance, but also its overall energy …

… Sources of clock skew in a VLSI chip may be unequal clock path delay, process variation, …
period in a digital VLSI chip. However, propagation delay in flip-flops is usually longer than …

… flip-flop which embodies the leak current cutoff mechanism. The RCSFF can reduce the clock
system power of a VLSI down to one-third compared to the conventional flip-flop. … total chip …

… IN many VLSI chips, the power dissipation of the clocking system, including … flipflops in
a chip. Thus, it is important to reduce power consumption in both the clock trees and the flip-flops. …

… The leekage current for our proposed flip flop, [12], [14] and a traditional masterslave D flip-flop
are 21nA, 25n, … Our pulse flipflop uses a novel pulse generator circuit. We compared our …

… bigger than the impact of the on-chip temperature gradient, in this paper, we only focus on
the impacts of aging and voltage drop in VLSI circuits. Therefore, it is necessary to find such …