Accelerating multicore architecture simulation using application profile

K Kimura, G Taguchi… - 2016 IEEE 10th …, 2016 - ieeexplore.ieee.org
Architecture simulators play an important role in exploring frontiers in the early stages of the
architecture design. However, the execution time of simulators increases with an increase …

ESESC: A fast multicore simulator using time-based sampling

EK Ardestani, J Renau - 2013 IEEE 19th International …, 2013 - ieeexplore.ieee.org
Architects rely on simulation in their exploration of the design space. However, slow
simulation speed caps their productivity and limits the depth of their exploration. Sampling …

Analytical-based high-level simulation of the microthreaded many-core architectures

I Uddin, R Poss, C Jesshope - 2014 22nd Euromicro …, 2014 - ieeexplore.ieee.org
High-level simulation is becoming commonly used for design space exploration of many-
core systems. We have been working on high-level simulation techniques for the …

Tss: Applying two-stage sampling in micro-architecture simulations

Z Yu, H Jin, J Chen, LK John - 2009 IEEE International …, 2009 - ieeexplore.ieee.org
Accelerating micro-architecture simulation is becoming increasingly urgent as the
complexity of workload and simulated processor increases. This paper presents a novel two …

PriME: A parallel and distributed simulator for thousand-core chips

Y Fu, D Wentzlaff - … on Performance Analysis of Systems and …, 2014 - ieeexplore.ieee.org
Modern processors are integrating an increasing number of cores, which brings new design
challenges. However, mainstream architectural simulators primarily focus on unicore or …

A dynamic computation method for fast and accurate performance evaluation of multi-core architectures

S Le Nours, A Postula… - 2014 Design, Automation …, 2014 - ieeexplore.ieee.org
Early estimation of performance has become necessary to facilitate design of complex multi-
core architectures. Performance evaluation based on extensive simulations is time …

Partitionsim: A parallel simulator for many-cores

S Jiao, D Wang, X Ye, W Xu, H Zhang… - 2012 IEEE 14th …, 2012 - ieeexplore.ieee.org
This paper introduces PartitionSim, a parallel simulator for future thousand-core processors.
The purpose of PartitionSim is to improve the simulation performance of many-core …

A hierarchical architecture description for flexible multicore system simulation

T Bruckschloegl, O Oey, M Rückauer… - … on Parallel and …, 2014 - ieeexplore.ieee.org
As processors and systems on chip in the embedded world increasingly become multicore,
parallel programming remains a difficult, time-consuming and complicated task. End users …

Virtual Manycore platforms: Moving towards 100+ processor cores

R Leupers, L Eeckhout, G Martin… - … , Automation & Test …, 2011 - ieeexplore.ieee.org
The evolution to Manycore platforms is real, both in the High-Performance Computing
domain and in embedded systems. If we start with ten or more cores, we can see the …

Statistical simulation of multithreaded architectures

JL Kihm, DA Connors - 13th IEEE International Symposium on …, 2005 - ieeexplore.ieee.org
Detailed, cycle-accurate processor simulation is an integral component of the design and
study of computer architectures. However, as the detail of simulation and processor design …