Heterogeneous integration to simplify many-core architecture simulations

R Poss, M Lankamp, MI Uddin, J Sýkora… - Proceedings of the 2012 …, 2012 - dl.acm.org
The EU Apple-CORE project has explored the design and implementation of novel general-
purpose many-core chips featuring hardware microthreading and hardware support for …

High-level simulation of concurrency operations in microthreaded many-core architectures

I Uddin - GSTF Journal on Computing (JoC), 2015 - Springer
Computer architects are always interested in analyzing the complex interactions amongst
the dynamically allocated resources. Generally a detailed simulator with a cycle-accurate …

One-IPC high-level simulation of microthreaded many-core architectures

I Uddin - The International Journal of High Performance …, 2017 - journals.sagepub.com
The microthreaded many-core architecture is comprised of multiple clusters of fine-grained
multi-threaded cores. The management of concurrency is supported in the instruction set …

Analytical-based high-level simulation of the microthreaded many-core architectures

I Uddin, R Poss, C Jesshope - 2014 22nd Euromicro …, 2014 - ieeexplore.ieee.org
High-level simulation is becoming commonly used for design space exploration of many-
core systems. We have been working on high-level simulation techniques for the …

PriME: A parallel and distributed simulator for thousand-core chips

Y Fu, D Wentzlaff - … on Performance Analysis of Systems and …, 2014 - ieeexplore.ieee.org
Modern processors are integrating an increasing number of cores, which brings new design
challenges. However, mainstream architectural simulators primarily focus on unicore or …

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

MI Uddin, CR Jesshope, MW van Tol… - Proceedings of the 2012 …, 2012 - dl.acm.org
The current many-core architectures are generally evaluated using cycle-accurate
simulations. However these detailed simulations of the architecture make the evaluation of …

[HTML][HTML] Multiple levels of abstraction in the simulation of microthreaded many-core architectures

I Uddin - Open Journal of Modelling and Simulation, 2015 - scirp.org
Simulators are generally used during the design of computer architectures. Typically,
different simulators with different levels of complexity, speed and accuracy are used …

Marss-x86: A qemu-based micro-architectural and systems simulator for x86 multicore processors

A Patel, F Afram, K Ghose - 1st International Qemu Users' Forum, 2011 - researchgate.net
Marss-x86 (Mico ARchitectural and System Simulator for x86) is an open-source full system
simulation framework developed at SUNY Binghamton for fast cycle-accurate simulation of …

SIMinG‐1k: A thousand‐core simulator running on general‐purpose graphical processing units

S Raghav, A Marongiu, C Pinto… - Concurrency and …, 2013 - Wiley Online Library
This paper introduces SIMinG‐1k—a manycore simulator infrastructure. SIMinG‐1k is a
graphics processing unit accelerated, parallel simulator for design‐space exploration of …

Cache-based high-level simulation of microthreaded many-core architectures

I Uddin, R Poss, C Jesshope - Journal of Systems Architecture, 2014 - Elsevier
The accuracy of simulated cycles in high-level simulators is generally less than the accuracy
in detailed simulators for a single-core systems, because high-level simulators simulate the …