FASE: FPGA acceleration of secure function evaluation
SU Hussain, F Koushanfar - 2019 IEEE 27th Annual …, 2019 - ieeexplore.ieee.org
We present FASE, an FPGA accelerator for Secure Function Evaluation (SFE) by employing
the well-known cryptographic protocol named Yao's Garbled Circuit (GC). SFE allows two …
the well-known cryptographic protocol named Yao's Garbled Circuit (GC). SFE allows two …
FASE: FPGA Acceleration of Secure Function Evaluation
SU Hussain, F Koushanfar - 2019 IEEE 27th Annual International …, 2019 - computer.org
We present FASE, an FPGA accelerator for Secure Function Evaluation (SFE) by employing
the well-known cryptographic protocol named Yao's Garbled Circuit (GC). SFE allows two …
the well-known cryptographic protocol named Yao's Garbled Circuit (GC). SFE allows two …
[引用][C] FASE: FPGA Acceleration of Secure Function Evaluation
SU Hussain, F Koushanfar - 2019 IEEE 27th Annual International …, 2019 - cir.nii.ac.jp
FASE: FPGA Acceleration of Secure Function Evaluation | CiNii Research CiNii 国立情報学
研究所 学術情報ナビゲータ[サイニィ] 詳細へ移動 検索フォームへ移動 論文・データをさがす 大学 …
研究所 学術情報ナビゲータ[サイニィ] 詳細へ移動 検索フォームへ移動 論文・データをさがす 大学 …
[PDF][PDF] FASE: FPGA Acceleration of Secure Function Evaluation
SU Hussain, F Koushanfar - researchgate.net
We present FASE, an FPGA accelerator for Secure Function Evaluation (SFE) by employing
the well-known cryptographic protocol named Yao's Garbled Circuit (GC). SFE allows two …
the well-known cryptographic protocol named Yao's Garbled Circuit (GC). SFE allows two …