Design and characterisation of 16× 1 parallel outputs SPAD array in 0.18 um CMOS technology

S Isaak - 2010 IEEE Asia Pacific Conference on Circuits and …, 2010 - ieeexplore.ieee.org
The design, simulation, fabrication, and characterisation of a silicon single photon
avalanche diode (SPAD) array with integral quenching and discriminator circuits is …
被引用次数：17 相关文章

Design and characterisation of 16× 1 parallel outputs SPAD array in 0.18 um CMOS technology

S Isaak, MC Pitter, S Bull, I Harrison - 2010 IEEE Asia Pacific Conference on … - infona.pl
The design, simulation, fabrication, and characterisation of a silicon single photon
avalanche diode (SPAD) array with integral quenching and discriminator circuits is …