[PDF][PDF] Soft error tolerance using HVDQ (Horizontal-Vertical-Diagonal-Queen parity method)
The likelihood of soft errors increases with system complexity, reduction in operational
voltages, exponential growth in transistors per chip, increases in clock frequencies and …
voltages, exponential growth in transistors per chip, increases in clock frequencies and …
Soft error tolerance using HVDQ (Horizontal-Vertical-Diagonal-Queen parity method)
S Ahammed, MS Sadi, MS Rahman, J Jürjens - 2017 - publica.fraunhofer.de
The likelihood of soft errors increases with system complexity, reduction in operational
voltages, exponential growth in transistors per chip, increases in clock frequencies and …
voltages, exponential growth in transistors per chip, increases in clock frequencies and …
Soft error tolerance using HVDQ (Horizontal-Vertical-Diagonal-Queen parity method).
S Ahammed, MS Sadi, MS Rahman… - … Systems Science & …, 2017 - search.ebscohost.com
The likelihood of soft errors increases with system complexity, reduction in operational
voltages, exponential growth in transistors per chip, increases in clock frequencies and …
voltages, exponential growth in transistors per chip, increases in clock frequencies and …