A 1.8–6.3 ghz quadrature ring vco-based fast-settling pll for wireline i/o in 55nm cmos
JS Gaggatur - 2021 34th International Conference on VLSI …, 2021 - ieeexplore.ieee.org
2021 34th International Conference on VLSI Design and 2021 20th …, 2021•ieeexplore.ieee.org
A wide-operating range quadrature ring voltage controlled oscillator (VCO) based phase
locked loop (PLL) having a phase frequency detector (PFD) with dead-zone removal and
current mismatch reduction techniques is presented in this work. The quadrature ring VCO is
capacitively-controlled and current-tuned to provide a 1.8 to 6.3 GHz operating range of
frequency making it appropriate for a wide variety of wireline and wireless applications. The
PLL prototype has been fabricated in a 55 nm CMOS process. The PLL has an active area of …
locked loop (PLL) having a phase frequency detector (PFD) with dead-zone removal and
current mismatch reduction techniques is presented in this work. The quadrature ring VCO is
capacitively-controlled and current-tuned to provide a 1.8 to 6.3 GHz operating range of
frequency making it appropriate for a wide variety of wireline and wireless applications. The
PLL prototype has been fabricated in a 55 nm CMOS process. The PLL has an active area of …
A wide-operating range quadrature ring voltage controlled oscillator (VCO) based phase locked loop (PLL) having a phase frequency detector (PFD) with dead-zone removal and current mismatch reduction techniques is presented in this work. The quadrature ring VCO is capacitively-controlled and current-tuned to provide a 1.8 to 6.3 GHz operating range of frequency making it appropriate for a wide variety of wireline and wireless applications. The PLL prototype has been fabricated in a 55 nm CMOS process. The PLL has an active area of 0.079 mm 2 , consumes a maximum power of 6.4 mW from 1.0 V supply and has a RMS jitter of 164 fs at 5 GHz.
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