A 12-GS/s phase-calibrated CMOS digital-to-analog converter for backplane communications
IEEE Journal of Solid-State Circuits, 2008•ieeexplore.ieee.org
A 12-GS/s 8-bit digital-to-analog converter (DAC) enables 24 Gb/s signaling over
conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies
an area of 670 μ m *\, 350 μ m and achieves INL and DNL of 0.31 and 0.28 LSB,
respectively. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and
35 dB at 1.5 GHz. Measured SDR and 3-dB bandwidth using 12 GS/s random data are 32
dB and 7.1 GHz, respectively. The power dissipation is 190 mW from 1-V and 1.8-V power …
conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies
an area of 670 μ m *\, 350 μ m and achieves INL and DNL of 0.31 and 0.28 LSB,
respectively. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and
35 dB at 1.5 GHz. Measured SDR and 3-dB bandwidth using 12 GS/s random data are 32
dB and 7.1 GHz, respectively. The power dissipation is 190 mW from 1-V and 1.8-V power …
A 12-GS/s 8-bit digital-to-analog converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 m 350 m and achieves INL and DNL of 0.31 and 0.28 LSB, respectively. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. Measured SDR and 3-dB bandwidth using 12 GS/s random data are 32 dB and 7.1 GHz, respectively. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.
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