A 23-GHz low-phase-noise digital bang–bang PLL for fast triangular and sawtooth chirp modulation

D Cherniak, L Grimaldi, L Bertulessi… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
D Cherniak, L Grimaldi, L Bertulessi, R Nonis, C Samori, S Levantino
IEEE Journal of Solid-State Circuits, 2018ieeexplore.ieee.org
This paper describes a 23-GHz digital bang-bang phase-locked loop (PLL) fabricated in 65-
nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented
circuit aims to generate a fast sawtooth chirp signal that grants significant advantages with
respect to the more conventional triangular waveform. Such a signal, however, features a
very large bandwidth that requires the adoption of a two-point injection scheme. This paper,
after intuitively discussing how the nonlinearity of the digitally controlled oscillator affects the …
This paper describes a 23-GHz digital bang-bang phase-locked loop (PLL) fabricated in 65-nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented circuit aims to generate a fast sawtooth chirp signal that grants significant advantages with respect to the more conventional triangular waveform. Such a signal, however, features a very large bandwidth that requires the adoption of a two-point injection scheme. This paper, after intuitively discussing how the nonlinearity of the digitally controlled oscillator affects the accuracy of frequency modulation, presents a novel automatic pre-distortion engine, operating fully in background, which linearizes the tuning characteristic. The 19.7-mA fractional-N PLL having an rms jitter of 213 fs and an in-band fractional spur of -58 dBc is capable of synthesizing fast chirps with 173-MHz/μs maximum slope and an idle time of less than 200 ns after an abrupt frequency step with no over or undershoot.
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