… Abstract—This paper describes a 3.6-Gb/s 27-mW transceiver … The transceiver operates at
3.6 Gb/s per port. Section II describes the system and signaling architecture of the transceiver. …

… allows a single transceiver design to be used in several applications. We present a low-power
I/O transceiver in 65 nm … Transceiver power reduction is enabled by passive equalization …

… fF to the I/O capacitance. This … I/O’s on some of these chips “failed” (exhibited 20% change
in characteristics) at levels higher than these, but we observed no outright failures in any I/O’s …

… transceiver systems, the memory bus width through TSV channels has significantly increased.
For instance, I/O … For instance, recent work utilizes baseband and multi-band transceiver to …

… I/O power dissipation. In this paper, we introduce novel circuit techniques [12] that reduce the
I/O … compared to the most recent memory bus I/O schemes. The demonstration chip, which …

… paying the cost of the extra clock I/O pins and channel, since the … even increasing the number
of channels and I/O pins. … Leblebici, “Hybrid NRZ/multi-tone serial data transceiver for multi…

… In this paper, a 12.3-mW 12.5-Gb/s transceiver complete transceiver … -speed I/O interface
circuits and clock and data recovery for wireline communication and backplane transceivers. …

… the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the
importance of high-speed low-power I/O links has also been increasing. Among proposed I/O …

… A block diagram of the transceiver core and multi-phase PLL is shown in Fig. 2. The transceiver
core has a transmitter block (TX) and receiver block (RX), which can be operated in the …

… I/O power efficiency has improved by an average of only 20% per year [2]. As a result, the total
I/O … circuits for high-speed I/O interfaces, frequency synthesizers, and RF transceivers. Mr. …