A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-tap DFE using soft decisions
KLJ Wong, A Rylyakov… - IEEE Journal of Solid-State …, 2007 - ieeexplore.ieee.org
KLJ Wong, A Rylyakov, CKK Yang
IEEE Journal of Solid-State Circuits, 2007•ieeexplore.ieee.orgA quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is
implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and
soft-decision technique is introduced to relax the timing critical feedback path of the DFE.
The shortened critical path enables better power performance. Error rates are below the
measurement capability of 10-12 with 2 31-1 PRBS at 6 Gb/s, with an 80-mV differential
launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws …
implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and
soft-decision technique is introduced to relax the timing critical feedback path of the DFE.
The shortened critical path enables better power performance. Error rates are below the
measurement capability of 10-12 with 2 31-1 PRBS at 6 Gb/s, with an 80-mV differential
launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws …
A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and soft-decision technique is introduced to relax the timing critical feedback path of the DFE. The shortened critical path enables better power performance. Error rates are below the measurement capability of 10 -12 with 2 31 -1 PRBS at 6 Gb/s, with an 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws 4.08 mA from a 1.0-V supply
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