A 75kb SRAM in 65nm CMOS for in-memory computing based neuromorphic image denoising
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020•ieeexplore.ieee.org
This paper presents an in-memory computing (IMC) architecture for image denoising. The
proposed SRAM based inmemory processing framework works in tandem with approximate
computing on a binary image generated from neuromorphic vision sensors. Implemented in
TSMC 65nm process, the proposed architecture enables 2000X energy savings ( 222X
from IMC) compared to a digital implementation when tested with the video recordings from
a DAVIS sensor and achieves a peak throughput of 1.25–1.66 frames/μs.
proposed SRAM based inmemory processing framework works in tandem with approximate
computing on a binary image generated from neuromorphic vision sensors. Implemented in
TSMC 65nm process, the proposed architecture enables 2000X energy savings ( 222X
from IMC) compared to a digital implementation when tested with the video recordings from
a DAVIS sensor and achieves a peak throughput of 1.25–1.66 frames/μs.
This paper presents an in-memory computing (IMC) architecture for image denoising. The proposed SRAM based inmemory processing framework works in tandem with approximate computing on a binary image generated from neuromorphic vision sensors. Implemented in TSMC 65nm process, the proposed architecture enables 2000X energy savings ( 222X from IMC) compared to a digital implementation when tested with the video recordings from a DAVIS sensor and achieves a peak throughput of 1.25 – 1.66 frames/μs.
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