As the microelectronics technology continuously scales down, the probability of multiple cell upsets (MCUs) induced by radiation in memory devices increases. It is required a robust error correction code (ECC), that has also an area, energy-efficient silicon implementation, to protect electronic devices from MCUs. This article describes the conception, implementation, and evaluation of a new algorithm called CLC, for the detection and correction of multiple errors in memories devices by using extended Hamming and parity bits. The rates of detection and correction of CLC are compared to other correction codes, as well as their implementation cost. The results demonstrated that the CLC has high correction efficiency for MCUs aligned with low area, energy, and delay overhead than the other evaluated codes.