A four-terabit packet switch supporting long round-trip times
IEEE Micro, 2003•ieeexplore.ieee.org
… We’ve designed our architecture to directly support a wide range of round-trip time
values in the switch fabric itself—a novel approach to the challenges of multiterabit-per-second
switching fabrics. We build our system from four different CMOS ASIC building blocks, using
a total of 40 chips for the switching core and 64 fabric interface chips on the line cards to
achieve an aggregate throughput of 4 Tbps. … We define the input round-trip time (iRTT) as
the composite of the transmission packet delay from an ingress fabric interface to a …
values in the switch fabric itself—a novel approach to the challenges of multiterabit-per-second
switching fabrics. We build our system from four different CMOS ASIC building blocks, using
a total of 40 chips for the switching core and 64 fabric interface chips on the line cards to
achieve an aggregate throughput of 4 Tbps. … We define the input round-trip time (iRTT) as
the composite of the transmission packet delay from an ingress fabric interface to a …
This 4-TBPS packet switch uses a combined input- and crosspoint-queued (CICQ) structure with virtual output queuing at the ingress to achieve the scalability of input-buffered switches, the performance of output-buffered switches, and low latency.
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