A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use
Proceedings of the Fifth IEEE International Caracas Conference on …, 2004•ieeexplore.ieee.org
We present an adder/substractor and a multiplier for single precision floating point numbers
in IEEE-754 format. They are fully synthesizable hardware descriptions in VHDL that are
available for general and educational use. Each one is presented in a single cycle and
pipelined implementation, suitable for high speed computing, with performance comparable
to other available implementations. Precision for non-denormal multiplications is under ulp
and for additions in/spl plusmn/1 LSB.
in IEEE-754 format. They are fully synthesizable hardware descriptions in VHDL that are
available for general and educational use. Each one is presented in a single cycle and
pipelined implementation, suitable for high speed computing, with performance comparable
to other available implementations. Precision for non-denormal multiplications is under ulp
and for additions in/spl plusmn/1 LSB.
We present an adder/substractor and a multiplier for single precision floating point numbers in IEEE-754 format. They are fully synthesizable hardware descriptions in VHDL that are available for general and educational use. Each one is presented in a single cycle and pipelined implementation, suitable for high speed computing, with performance comparable to other available implementations. Precision for non-denormal multiplications is under ulp and for additions in /spl plusmn/1 LSB.
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