presented. The proposed configuration features high input swing, gain tunability, wide-
bandwidth, and low design complexity. The concept is validated with simulation results in
Cadence Virtuoso using SCL 0.18-μm technology parameters. Using a±0.9 V power supply,
the buffer with a gain of 1, can drive a 1 V p− p sinusoid into a 50 Ω load with a THD of better
than 0.015%, with a 3-dB bandwidth of 1.55 GHz and consumes 9 mW. The proposed …