A performance analysis of classified binary adder architectures and the VHDL simulations
A Sertbaş, R selami Özbey - IU-Journal of Electrical & Electronics …, 2004 - dergipark.org.tr
A Sertbaş, R selami Özbey
IU-Journal of Electrical & Electronics Engineering, 2004•dergipark.org.trIn this paper, the four binary adder architectures belong to a different adder class are studied
and compared with each other to analyse their performances. Comparisons include the unit-
gate models for area and delay. As the performance measure, the product of the area and
the delay is used. By a VHDL simulator, the adder structures are simulated to verify the
functional correctness and to measure delay times
and compared with each other to analyse their performances. Comparisons include the unit-
gate models for area and delay. As the performance measure, the product of the area and
the delay is used. By a VHDL simulator, the adder structures are simulated to verify the
functional correctness and to measure delay times
In this paper, the four binary adder architectures belong to a different adder class are studied and compared with each other to analyse their performances. Comparisons include the unit-gate models for area and delay. As the performance measure, the product of the area and the delay is used. By a VHDL simulator, the adder structures are simulated to verify the functional correctness and to measure delay times
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