A reconfigurable pipelined architecture for convolutional neural network acceleration

C Xue, S Cao, R Jiang, H Yang - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
C Xue, S Cao, R Jiang, H Yang
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018ieeexplore.ieee.org
The convolutional neural network (CNN) has become widely used in a variety of vision
recognition applications, and the hardware acceleration of CNN is in urgent need as
increasingly more computations are required in the state-of-the-art CNN networks. In this
paper, we propose a pipelined architecture for CNN acceleration. The probability of both
inner-layer and inter-layer pipeline for typical CNN networks is analyzed. And two types of
data re-ordering methods, the filter-first (FF) flow and the image-first (IF) flow, are proposed …
The convolutional neural network (CNN) has become widely used in a variety of vision recognition applications, and the hardware acceleration of CNN is in urgent need as increasingly more computations are required in the state-of-the-art CNN networks. In this paper, we propose a pipelined architecture for CNN acceleration. The probability of both inner-layer and inter-layer pipeline for typical CNN networks is analyzed. And two types of data re-ordering methods, the filter-first (FF) flow and the image-first (IF) flow, are proposed for different kinds of layers. Then, a pipelined CNN accelerator for AlexNet is implemented, the dataflow of which can be reconfigurably selected for different layer processing. Simulation results show that the proposed pipelined architecture achieves 43% performance improvement compared with the non-pipelined ones. The AlexNet accelerator is implemented in 65nm CMOS technology working at 200MHz, with 350mW power consumption and 24GFLOPS peak performance.
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