A survey on power gating techniques in low power VLSI design

G Srikanth, BM Bhaskara, M Asha Rani - Information Systems Design and …, 2016 - Springer
G Srikanth, BM Bhaskara, M Asha Rani
Information Systems Design and Intelligent Applications: Proceedings of Third …, 2016Springer
The most effective technique to reduce dynamic power is the supply voltage reduction by
technology scaling which reduces threshold voltage. Under deep submicron technology,
reduction in threshold voltage increases leakage currents, gate tunneling currents and
leakage power in standby mode. Most of the handheld devices have long standby mode
cause leakage current contributing to leakage power dissipation. In this paper, various
leakage power reductions, charge recycling techniques, data retention of memories. Various …
Abstract
The most effective technique to reduce dynamic power is the supply voltage reduction by technology scaling which reduces threshold voltage. Under deep submicron technology, reduction in threshold voltage increases leakage currents, gate tunneling currents and leakage power in standby mode. Most of the handheld devices have long standby mode cause leakage current contributing to leakage power dissipation. In this paper, various leakage power reductions, charge recycling techniques, data retention of memories. Various Power gating techniques are discussed in detail.
Springer
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