thanks to binarized parameters. Several researchers have proposed the compute-in-
memory (CiM) SRAMs for XNOR-and-accumulation computations (XACs) in BNNs by
adding additional transistors to the conventional 6T SRAM, which reduce the latency and
energy of the data movements. However, due to the additional transistors, the CiM SRAMs
suffer from larger area and longer wires than the conventional 6T SRAMs. Meanwhile …