An 8-bit 10-GHz 8× time-interleaved successive-approximation-register (SAR) analog-to-
digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter
(DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in
the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of
gradient on the proposed DAC layout. The DAC additionally implements quantized sub-
radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch …

An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an
aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford
a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped
switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by
more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21
mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar …