An analog CMOS chip set for neural networks with arbitrary topologies
JA Lansner, T Lehmann - IEEE Transactions on Neural …, 1993 - ieeexplore.ieee.org
JA Lansner, T Lehmann
IEEE Transactions on Neural Networks, 1993•ieeexplore.ieee.orgAn analog CMOS chip set for implementations of artificial neural networks (ANNs) has been
fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a
synapse chip. Neurons on the neuron chips can be interconnected at random via synapses
on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test
chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions
which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a …
fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a
synapse chip. Neurons on the neuron chips can be interconnected at random via synapses
on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test
chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions
which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a …
An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4*4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 mu s per layer.< >
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