This paper presents a scan path design to ease the controllability and observability of self-timed logic. The scan path registers operate in asynchronous mode during operation and test. Therefore, no synchronous test clock is necessary during the test mode. New test control modules provide the control sequences to switch between the parallel data path and the serial scan path. In addition to the data path, the control path and the bundled data interface is integrated into the test concept. The new scan path register has been developed with low area overhead and a small additional delay in the critical data path. An example is used to verify this DFT modules for the data and the control path. It demonstrates the functionality during test and operational mode and the compact realization of the asynchronous scan register.