Architectures and VLSI implementations of the AES-proposal Rijndael
N Sklavos, O Koufopavlou - IEEE Transactions on computers, 2002 - ieeexplore.ieee.org
IEEE Transactions on computers, 2002•ieeexplore.ieee.org
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented
in this paper. These alternative architectures are operated both for encryption and
decryption process. They reduce the required hardware resources and achieve high-speed
performance. Their design philosophy is completely different. The first uses feedback logic
and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications
with low covered area resources. The second architecture is optimized for high-speed …
in this paper. These alternative architectures are operated both for encryption and
decryption process. They reduce the required hardware resources and achieve high-speed
performance. Their design philosophy is completely different. The first uses feedback logic
and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications
with low covered area resources. The second architecture is optimized for high-speed …
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications with low covered area resources. The second architecture is optimized for high-speed performance using pipelined technique. Its throughput can reach 3.65 Gbit/sec.
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